GATE CS I/O Interface: Interrupt and DMA Mode questions

Consider the following two statements about interrupt handling mechanisms in a CPU. $\text{S1}$: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism. $\text{S2}$: In daisy-chain interrupt mechanism, the CPU polls all the input devices …

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the …

​​​​Which one of the following statements is FALSE?

​​​Consider a computer with a $4 \mathrm{MHz}$ processor. Its $\text{DMA}$ controller can transfer $8$ bytes in $1$ cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the $\text{DMA}$ controller if $1 \%$ of the processor cycles are used for …

A keyboard connected to a computer is used at a rate of $1$ keystroke per second. The computer system polls the keyboard every $10 \mathrm{~ms}$ (milli seconds) to check for a keystroke and consumes $100\; \mu \mathrm{s}$ (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional …

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ processor. If $0.5 \%$ processor cycles are used for $\text{DMA}$, the data transfer rate of the device is …

Consider the following statements. Daisy chaining is used to assign priorities in attending interrupts. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. In polling, the CPU periodically checks the status bits to know if any device needs its attention. During DMA, both the CPU and DMA controller can be bus …

The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the $\text{DMA}$ controller needs to get the control of the system bus from the processor to transfer the file from …

On a non-pipelined sequential processor, a program segment, which is the part of the interrupt service routine, is given to transfer $500$ bytes from an I/O device to memory. Initialize the address register Initialize the count to 500 LOOP: Load a byte from device Store in memory at address given by address register Increment the address register Decrement …

A CPU generally handles an interrupt by executing an interrupt service routine:

Which of the following statements about synchronous and asynchronous I/O is NOT true?

Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ are the general purpose registers. …

Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ are the general purpose registers. …

Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ are the general purpose registers. …

A device with data transfer rate $10$ KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $4\mu$sec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under …

Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a $4$ byte word from the …

A hard disk with a transfer rate of $10$ Mbytes/second is constantly transferring data to memory using DMA. The processor runs at $600$ MHz, and takes $300$ and $900$ clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is $20$ Kbytes, what is the percentage of processor time consumed for the transfer …

A device employing INTR line for device interrupt puts the CALL instruction on the data bus while:

Which of the following is true?