GATE CS Computer Organization and Architecture questions

Practise Computer Organization and Architecture questions for GATE CS. Explore official PYQs and original subject-wise quizzes, check answers and view available solutions. Free, no sign-in.

Track address sizes, cache organisation and pipeline dependencies carefully. Write down the units and assumptions before computing memory access times or processor performance.

20 on this page

SubjectTopicYearType

Match each addressing mode in

\textbf{List I}

with a data element or an element of a data structure (in a high-level language) in

\textbf{List II}

Consider a processor

\text{P}

whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand. Which one of the following sequences of instructions corresponds to the high-level language statement

\mathrm{Z}=\mathrm{X}+\mathrm{Y}

? Note: X, Y, and Z …

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

The size of the physical address space of a processor is

2^{32}

bytes. The capacity of a cache memory unit is

2^{23}

bytes. The cache block size is

128

bytes. The cache memory unit can be built as a direct mapped cache or as a

K

-way set-associative cache, where

K=2^{L}

L \in\{1,2,3\}

. Let the length of the TAG field be

M

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid. For a given memory reference, which of the …

Consider a hard disk with a rotational speed of

15000

rpm. The time to move the read/write head from a track to its adjacent track is

1

millisecond. Initially, the head is on track

0

. The number of sectors per track is

400

. The sector size is

1024

bytes. It is necessary to transfer data from

10

randomly located sectors in each of the …

The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let

t_{E X}

denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of

t_{E X}

M

(the number of instructions of that …

Consider the following two statements about interrupt handling mechanisms in a CPU.

\text{S1}

: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.

\text{S2}

: In daisy-chain interrupt mechanism, the CPU polls all the input devices …

Consider a processor that has

16

general purpose registers and it uses

2

-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has

2

register operands and a

6

-bit immediate operand. Each Rtype instruction has …

Consider a system with a processor and a

4

KB direct mapped cache with block size of

16

bytes. The system has a

16

MB physical memory. Four words

\mathrm{P}, \mathrm{Q}, \mathrm{R}

, and S are accessed by the processor in the same order

10

times. That is, there are a total of

40

memory references in the sequence …

To keep track of free blocks in a file system, one of the two approaches is generally used - using bitmaps (bit vectors) or using linked lists. Consider that the linked list approach is used to keep track of free blocks in a file system. Assume that the disk size is

16

GB , block size is

2

KB , and block numbers used are

32

-bit long. A single …

A non-pipelined instruction execution unit that operates at

1.6

GHz clock takes an average of

5

clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at

1.2

GHz due to pipeline …

Consider a system with

1

MB physical memory and a word length of

1

byte. The system uses a direct mapped cache, with block numbers starting from

0

. The word with physical address

\text{0xA2C28}

is mapped to the cache block number

17610

. The maximum possible size of the cache (in KB ) for this configuration is

\_\_\_\_\_\_\_

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the …

A partial data path of a processor is given in the figure, where

\text{RA, RB,}

\text{RZ}

32

-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

Consider a memory system with

1 \mathrm{M}

bytes of main memory and

16 \mathrm{~K}

bytes of cache memory. Assume that the processor generates

20

-bit memory address, and the cache block size is

16

bytes. If the cache uses direct mapping, how many bits will be required to store all the

\operatorname{tag}

values? [Assume memory is byte …

A processor has

64

general-purpose registers and

50

distinct instruction types. An instruction is encoded in

32

-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?

\text{ADD R1}

\#25

\text{R 1=R 1+25}

A computer has a memory hierarchy consisting of two-level cache

\text{(L1}

\text{L2)}

and a main memory. If the processor needs to access data from memory, it first looks into

\text{L1}

cache. If the data is not found in

\text{L1}

cache, it goes to

\text{L2}

cache. If it fails to get the data from

\text{L2}

cache, it goes to main …

Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is

1

nanosecond (ns) and the "hit rate" for L1 cache is

90 \%

while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the "hit rate" is

80 \%

and the "miss penalty" for transferring …

5

-stage instruction pipeline has stage delays of

180,250,150,170

250

, respectively, in nanoseconds. The delay of an inter-stage latch is

10

nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process

1000

instructions in microseconds is __________. (rounded off to two decimal …