GATE CS 2025 Set 1 Q17 — ALU, Data-path and Control Unit

Based on the given partial data path of the processor:

• The ALU has two inputs, each preceded by a multiplexer (MUX) that selects the operand source.
• MUX 1 (at the first ALU input) can select between the output of register $\text{RA}$ and an immediate value.
• MUX 2 (at the second ALU input) can select between the output of register $\text{RB}$ and an immediate value.

By configuring the control signals of these multiplexers, we can achieve the following combinations of operands for the ALU:

1. Two Registers: Selecting register $\text{RA}$ from MUX 1 and register $\text{RB}$ from MUX 2 allows arithmetic operations involving two registers. Thus, Option A is correct.
2. One Register and One Immediate Value: Selecting register $\text{RA}$ (or $\text{RB}$) from one MUX and an immediate value from the other MUX allows arithmetic operations involving one register and one immediate value. Thus, Option B is correct.
3. Two Immediate Values: Selecting immediate values from both MUX 1 and MUX 2 allows arithmetic operations involving two immediate values. Thus, Option C is correct.

Since the data path can perform all three types of operations, Option D is incorrect.