GATE CS 2005 Q80 — ALU, Data-path and Control Unit

At the start of the execution cycle, the first word of the instruction has already been fetched, and the $\text{PC}$ has been incremented to point to the second word (which contains the address sub).

To execute the instruction, we need to perform two operations:

1. $\text{Rn} \leftarrow \text{PC} + 1$
2. $\text{PC} \leftarrow \text{M[PC]}$

This can be achieved in the minimum number of clock cycles as follows:

• Cycle 1: Load the address of the second word into the $\text{MAR}$ to initiate the memory read.
  $$\text{MAR} \leftarrow \text{PC}$$ (This uses the internal CPU bus to transfer the value of $\text{PC}$ to $\text{MAR}$. Memory read starts.)
• Cycle 2: Complete the memory read and simultaneously perform the register increment.
  $$\text{MDR} \leftarrow \text{M[MAR]}\quad \text{and} \quad \text{Rn} \leftarrow \text{PC} + 1$$ (The memory read uses the external memory bus to load $\text{MDR}$. Since the internal CPU bus is free, $\text{PC}$ is placed on it, incremented by the $\text{ALU}$, and the result is stored in $\text{Rn}$.)
• Cycle 3: Update the $\text{PC}$ with the target address loaded into $\text{MDR}$.
  $$\text{PC} \leftarrow \text{MDR}$$ (This transfers the target address from $\text{MDR}$ to $\text{PC}$ via the internal CPU bus.)

Thus, the minimum number of CPU clock cycles needed during the execution cycle is 3.