GATE CS 2020 Q4 — ALU, Data-path and Control Unit

To execute the instruction $R0 \leftarrow R1 + R2$, the processor must perform the instruction cycle phases in the following sequence:

1. Instruction Fetch (IF):
   • First, the address in the Program Counter ($PC$) is transferred to the Memory Address Register ($MAR$), and a memory read operation is initiated:
     Step 3: $PC_{r}, \text{ MAR}_{w}, \text{ MEM}_{r}$
   • Once the instruction is fetched from memory into the Memory Data Register ($MDR$), it is loaded into the Instruction Register ($IR$):
     Step 5: $\text{ MDR}_{r}, \text{ IR}_{w}$
2. Instruction Decode & Execution:
   • In a standard single-bus data path, the ALU cannot receive two operands directly from the bus simultaneously. Thus, one operand ($R1$) is first read and stored in a temporary register ($\text{TEMP1}$):
     Step 2: $R1_{r}, \text{ TEMP1}_{w}$
   • Next, the second operand ($R2$) is placed on the bus, the value in $\text{TEMP1}$ is read, both are added by the ALU, and the result is stored in $\text{TEMP2}$:
     Step 1: $R2_{r}, \text{ TEMP1}_{r}, ALU_{\text{add}}, \text{ TEMP2}_{w}$
   • Finally, the result stored in $\text{TEMP2}$ is written back to the destination register $R0$:
     Step 4: $\text{ TEMP2}_{r}, \text{ R0}_{w}$

Combining these steps in order gives: $3 \rightarrow 5 \rightarrow 2 \rightarrow 1 \rightarrow 4$.

Therefore, the correct option is C.