GATE CS 2026 Set 1 Q6 — Pipeline Hazards

A data hazard occurs when instructions that overlap in execution have data dependencies, and the pipeline must be stalled or bypassed to ensure correct execution.

Let's analyze the given dependencies between two instructions, $I_1$ (earlier) and $I_2$ (later):

1. Read-After-Write (RAW) / True Dependency:

   $I_2$ tries to read a register before $I_1$ writes to it. If $I_2$ reads the register before $I_1$ updates it, it will receive the old (incorrect) value. This is a true data dependency and causes a data hazard in almost all pipelined processors (including standard in-order pipelines).

2. Write-After-Read (WAR) / Anti-Dependency:

   $I_2$ tries to write to a register before it is read by $I_1$. In a standard in-order pipeline, reads occur in an early stage (e.g., Instruction Decode) and writes occur in a late stage (e.g., Write Back), so $I_1$ always reads the value before $I_2$ overwrites it. Thus, WAR does not cause a hazard in standard in-order pipelines.

3. Write-After-Write (WAW) / Output Dependency:

   $I_2$ tries to write to a register before $I_1$ writes to it. In an in-order pipeline, writes happen in program order, so this does not cause a hazard.

4. Read-After-Read (RAR):

   Both instructions only read the register. Since no instruction modifies the register value, no hazard can ever occur.

Thus, Read-after-write (RAW) is the dependency that causes a data hazard in a pipelined processor.