GATE CS 2015 Set 3 Q47 — Pipeline Hazards

To determine the correctness of the statements, let us first identify the registers read and written by each instruction in the sequence:

• $I_1$: Reads $\{R2, R3\}$, Writes to $\{R1\}$
• $I_2$: Reads $\{R1, R3\}$, Writes to $\{R7\}$
• $I_3$: Reads $\{R1, R5\}$, Writes to $\{R4\}$
• $I_4$: Reads $\{R2, R4\}$, Writes to $\{R3\}$
• $I_5$: Reads $\{R8, R9\}$, Writes to $\{R7\}$

An anti-dependence (Write-After-Read / WAR) exists between instruction $I_i$ and a subsequent instruction $I_j$ ($i < j$) if $I_j$ writes to a register that is read by $I_i$.

Analyzing the Statements:

S1: There is an anti-dependence between instructions $I_2$ and $I_5$

• $I_2$ reads $\{R1, R3\}$.
• $I_5$ writes to $\{R7\}$.
• There is no register read by $I_2$ and written by $I_5$. (Note: Both write to $R7$, which is an output dependence / WAW, not an anti-dependence).
• Therefore, S1 is False.

S2: There is an anti-dependence between instructions $I_2$ and $I_4$

• $I_2$ reads $\{R1, R3\}$.
• $I_4$ writes to $\{R3\}$.
• Since $I_2$ reads $R3$ before $I_4$ writes to $R3$, there is a WAR (anti-dependence) between $I_2$ and $I_4$.
• Therefore, S2 is True.

S3: Within an instruction pipeline an anti-dependence always creates one or more stalls

• In a standard in-order pipeline, registers are read in an early stage (e.g., Instruction Decode - ID) and written in a later stage (e.g., Write Back - WB). Because instructions execute in order, the read by $I_2$ naturally completes before the write by $I_4$ occurs. Thus, no stalls are needed.
• In out-of-order processors, techniques like register renaming are used to eliminate anti-dependencies entirely without introducing any stalls.
• Therefore, anti-dependence does not always create stalls, making S3 is False.

Conclusion:

Only statement S2 is true. Hence, the correct option is B.