GATE CS Pipeline Hazards questions

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let $t_{E X}$ denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of $t_{E X}$ and $M$ (the number of instructions of that …

A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ of one without any pipeline hazards. For a given program $\text{P}$ that has $30 \%$ branch instructions, control hazards incur $2$ cycles stall for every branch. A new …

Consider the following code sequence having five instructions from $I_1 \text{ to } I_5$. Each of these instructions has the following format. OP Ri, Rj, Rk Where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri. $I_1$: ADD R1, R2, R3 $I_2$: MUL R7, R1, R3 $I_3$: SUB R4, R1, R5 $I_4$: ADD R3, R2, …