GATE CS 2026 Set 1 Q50 — Pipeline Hazards

The pipeline clock cycle is $1\text{ ns}$. Since the EX stage is not pipelined internally, an instruction with execution time $t_{EX}$ will occupy the EX stage for $\lceil t_{EX} \rceil$ clock cycles.

In a standard pipeline, each instruction is expected to spend $1$ clock cycle in the EX stage. Any additional cycles spent by an instruction in the EX stage prevent subsequent instructions from entering, thereby causing structural hazard stalls. Thus, the number of stall cycles introduced by a single instruction is:

We calculate the total stall cycles for each instruction type as follows:

• LOAD: $t_{EX} = 1.8\text{ ns} \implies \lceil 1.8 \rceil = 2$ cycles. Stall $= 2 - 1 = 1$ cycle.
  Total stalls $= 15 \times 1 = 15$
• IMUL: $t_{EX} = 1.5\text{ ns} \implies \lceil 1.5 \rceil = 2$ cycles. Stall $= 2 - 1 = 1$ cycle.
  Total stalls $= 10 \times 1 = 10$
• IDIV: $t_{EX} = 2.5\text{ ns} \implies \lceil 2.5 \rceil = 3$ cycles. Stall $= 3 - 1 = 2$ cycles.
  Total stalls $= 5 \times 2 = 10$
• FADD: $t_{EX} = 1.7\text{ ns} \implies \lceil 1.7 \rceil = 2$ cycles. Stall $= 2 - 1 = 1$ cycle.
  Total stalls $= 10 \times 1 = 10$
• FSUB: $t_{EX} = 1.7\text{ ns} \implies \lceil 1.7 \rceil = 2$ cycles. Stall $= 2 - 1 = 1$ cycle.
  Total stalls $= 5 \times 1 = 5$
• FMUL: $t_{EX} = 2.8\text{ ns} \implies \lceil 2.8 \rceil = 3$ cycles. Stall $= 3 - 1 = 2$ cycles.
  Total stalls $= 15 \times 2 = 30$
• FDIV: $t_{EX} = 3.2\text{ ns} \implies \lceil 3.2 \rceil = 4$ cycles. Stall $= 4 - 1 = 3$ cycles.
  Total stalls $= 5 \times 3 = 15$
• Others: $t_{EX} < 1.0\text{ ns} \implies 1$ cycle. Stall $= 1 - 1 = 0$ cycles.
  Total stalls $= 35 \times 0 = 0$

Summing these values gives the total number of stall cycles: