GATE CS 2026 Set 1 Q5 — Machine Instructions and Addressing Modes

In a load-store architecture (such as RISC), arithmetic and logical instructions (like ADD) cannot directly access memory operands. They can only operate on processor registers. Memory access is strictly restricted to dedicated LOAD and STORE instructions.

Let's analyze the given high-level statement: $Z = X + Y$, where $X$, $Y$, and $Z$ are memory operands.

1. Load $X$ into a register:
   LOAD R0, X (loads the value of memory location $X$ into register $R0$)
2. Load $Y$ into another register:
   LOAD R1, Y (loads the value of memory location $Y$ into register $R1$)
3. Perform the addition using registers:
   ADD R2, R0, R1 (computes $R2 = R0 + R1$)
4. Store the result back to memory location $Z$:
   STORE Z, R2 (stores the value of register $R2$ into memory location $Z$)

Evaluating the options:

• Option A: ADD Z, X, Y attempts to perform addition directly on memory operands, which is invalid in a load-store architecture.
• Option B: ADD Z, R0, Y attempts to use memory operands $Z$ and $Y$ directly in an ADD instruction, which is invalid.
• Option C: ADD R0, X, Y attempts to use memory operands $X$ and $Y$ directly in an ADD instruction, which is invalid.
• Option D: Correctly adheres to the load-store architecture constraints by loading operands into registers first, performing the addition on registers, and then storing the result back to memory.