GATE CS 2026 Set 2 Q8 — I/O Interface: Interrupt and DMA Mode

To determine the correctness of the statements, let us analyze each one:

Statement S1:

• Vectored Interrupts: The interrupting device directly provides the interrupt vector (or its address) to the CPU. This allows the CPU to immediately load the program counter with the ISR address and start execution.
• Non-Vectored Interrupts: The CPU branches to a single, predefined memory address. From there, a software routine (polling) must run to identify which device raised the interrupt before branching to its specific ISR. This additional software overhead increases the latency to start the actual ISR.

Thus, S1 is True.

Statement S2:

• Daisy-Chain Mechanism: This is a hardware-based priority resolution technique. When an interrupt occurs, the CPU sends an Interrupt Acknowledge ($\text{INTA}$) signal. This signal propagates serially through the devices connected in a chain. The highest-priority device that requested the interrupt intercepts the signal and places its vector address on the data bus.
• The CPU does not poll the devices individually in a daisy-chain setup; the hardware structure itself determines the source. Individual polling is done in software-based polling schemes.

Thus, S2 is False.

Therefore, $\text{S1}$ is true and $\text{S2}$ is false.