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Official PYQ · 2024

GATE CS 2024 Set 2 Q1 — I/O Interface: Interrupt and DMA Mode

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​​​Consider a computer with a 4MHz4 \mathrm{MHz} processor. Its DMA\text{DMA} controller can transfer 88 bytes in 11 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA\text{DMA} controller if 1%1 \% of the processor cycles are used for DMA\text{DMA}?

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Answer: C

To find the data transfer rate of the DMA controller in bits per second, we can break down the calculation into the following steps:

  1. Determine the total processor cycles per second:

    Processor frequency=4 MHz=4×106 cycles/second\text{Processor frequency} = 4 \text{ MHz} = 4 \times 10^6 \text{ cycles/second}

  2. Calculate the cycles stolen by the DMA controller per second:

    Since 1%1\% of the processor cycles are used for DMA, the number of cycles available for DMA per second is:

    DMA cycles per second=1% of (4×106)=0.01×4,000,000=40,000 cycles/second\text{DMA cycles per second} = 1\% \text{ of } (4 \times 10^6) = 0.01 \times 4,000,000 = 40,000 \text{ cycles/second}

  3. Calculate the data transferred in bytes per second:

    The DMA controller transfers 88 bytes in each stolen cycle:

    Data transfer rate (in bytes/sec)=40,000 cycles/second×8 bytes/cycle=320,000 bytes/second\text{Data transfer rate (in bytes/sec)} = 40,000 \text{ cycles/second} \times 8 \text{ bytes/cycle} = 320,000 \text{ bytes/second}

  4. Convert the data transfer rate to bits per second:

    Since 1 byte=8 bits1 \text{ byte} = 8 \text{ bits}:

    Data transfer rate (in bits/sec)=320,000×8=2,560,000 bits/second\text{Data transfer rate (in bits/sec)} = 320,000 \times 8 = 2,560,000 \text{ bits/second}

Using the Indian numbering system representation, 2,560,0002,560,000 is written as 25,60,00025,60,000.

Therefore, the correct option is C.

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