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Official PYQ · 2021Set 2 · Q20I/O Interface: Interrupt and DMA ModeNAT1 mark

GATE CS 2021 Set 2 Q20 — I/O Interface: Interrupt and DMA Mode

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Consider a computer system with DMA\text{DMA} support. The DMA\text{DMA} module is transferring one 88-bit character in one CPU\text{CPU} cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz\text{2 MHz} processor. If 0.5%0.5 \% processor cycles are used for DMA\text{DMA}, the data transfer rate of the device is __________ bits per second.

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Answer: 80000 : 80000

To find the data transfer rate of the device in bits per second, we calculate the number of CPU cycles allocated to the DMA module per second.

1. Given Data:

  • Processor frequency = 2 MHz=2×106 cycles per second2 \text{ MHz} = 2 \times 10^6 \text{ cycles per second}
  • Percentage of processor cycles used for DMA = 0.5%0.5\%
  • Data transferred per DMA cycle = 1 character=8 bits1 \text{ character} = 8 \text{ bits}

2. Calculation:

First, calculate the number of CPU cycles stolen by the DMA module per second:

DMA cycles per second=0.5% of (2×106 cycles/sec)\text{DMA cycles per second} = 0.5\% \text{ of } (2 \times 10^6 \text{ cycles/sec})DMA cycles per second=0.5100×2×106=10,000 cycles/sec\text{DMA cycles per second} = \frac{0.5}{100} \times 2 \times 10^6 = 10,000 \text{ cycles/sec}

Since the DMA module transfers 88 bits of data in each cycle, the total data transfer rate is:

Data transfer rate=10,000 cycles/sec×8 bits/cycle=80,000 bits/second\text{Data transfer rate} = 10,000 \text{ cycles/sec} \times 8 \text{ bits/cycle} = 80,000 \text{ bits/second}

Thus, the data transfer rate of the device is 80000 bits per second.

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