GATE CS 2026 Set 2 Q47 — Instruction Pipelining

To find the speed-up obtained by the pipelined design over the non-pipelined design, we compare the average execution time per instruction for both configurations.

1. Non-Pipelined System

• Clock Frequency ($f_{\text{np}}$): $1.6\text{ GHz}$
• Clock Cycle Time ($T_{\text{np}}$): $\frac{1}{1.6\text{ GHz}} = \frac{1}{1.6}\text{ ns}$
• Average Cycles Per Instruction ($CPI_{\text{np}}$): $5$
• Average Execution Time per Instruction ($ET_{\text{np}}$): $$ET_{\text{np}} = CPI_{\text{np}} \times T_{\text{np}} = 5 \times \frac{1}{1.6}\text{ ns} = 3.125\text{ ns}$$

2. Pipelined System

• Clock Frequency ($f_{\text{p}}$): $1.2\text{ GHz}$
• Clock Cycle Time ($T_{\text{p}}$): $\frac{1}{1.2\text{ GHz}} = \frac{1}{1.2}\text{ ns}$
• Average Cycles Per Instruction ($CPI_{\text{p}}$): Under ideal conditions, the pipeline achieves $1$ instruction per clock cycle (Ideal $CPI = 1$). Since $30\%$ of the instructions encounter a stall of $2$ cycles: $$CPI_{\text{p}} = \text{Ideal CPI} + \text{Average Stall Cycles} = 1 + (0.30 \times 2) = 1.6$$
• Average Execution Time per Instruction ($ET_{\text{p}}$): $$ET_{\text{p}} = CPI_{\text{p}} \times T_{\text{p}} = 1.6 \times \frac{1}{1.2}\text{ ns} = \frac{1.6}{1.2}\text{ ns} = \frac{4}{3}\text{ ns} \approx 1.333\text{ ns}$$

3. Speed-up Calculation

The speed-up ($S$) is given by the ratio of the execution times:

Rounding off to two decimal places, the speed-up obtained is $2.34$ (which lies within the accepted range of $2.30$ to $2.40$).