Consider a -stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?
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Answer: A;B;C
Let us analyze each statement regarding data forwarding in a 5-stage pipeline:
- Correct: Forwarding (or bypassing) is a technique where the intermediate result from a source stage of an earlier instruction (such as EX or MEM) is routed directly to the destination stage of a dependent later instruction (typically EX) before it is written back to the register file.
- Correct: In a load-use scenario, the loaded data becomes available at the output of the MEM stage. This data can be forwarded directly to the input of the EX stage of the next instruction, minimizing the stall penalty to just 1 cycle.
- Correct: Forwarding cannot eliminate all stalls. For example, in a load-use hazard where a load instruction is immediately followed by an instruction that depends on it, a 1-cycle stall is unavoidable because the data is needed at the start of the EX stage of the dependent instruction but is only ready at the end of the MEM stage of the load instruction.
- Incorrect: Forwarding requires significant extra hardware, including bypass buses (wires), multiplexers at the ALU inputs to select the forwarded data, and control logic to detect hazards and generate selection signals.
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