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Official PYQ · 2024Set 2 · Q21Instruction PipeliningMCQ1 mark

GATE CS 2024 Set 2 Q21 — Instruction Pipelining

Explain with AI

​​​​​An instruction format has the following structure:

Instruction Number: Opcode destination reg, source reg-11, source reg-22
 

Consider the following sequence of instructions to be executed in a pipelined processor:

I 1: DIV R3, R1, R2\text{I 1: DIV R3, R1, R2}

I 2: SUB R5, R3, R4\text{I 2: SUB R5, R3, R4}

I 3: ADD R3, R5, R6\text{I 3: ADD R3, R5, R6}

I 4: MUL R7, R3, R8\text{I 4: MUL R7, R3, R8}

Which of the following statements is/are TRUE?

Choose one option
View worked solution

Answer: A

To identify the dependencies, let us first list the destination and source registers for each instruction based on the format Opcode destination, source-1, source-2:

  • I1: DIV R3, R1, R2 → Writes to R3, Reads from R1, R2
  • I2: SUB R5, R3, R4 → Writes to R5, Reads from R3, R4
  • I3: ADD R3, R5, R6 → Writes to R3, Reads from R5, R6
  • I4: MUL R7, R3, R8 → Writes to R7, Reads from R3, R8

Now, let us evaluate each option:

  1. There is a RAW dependency on R3 between I1 and I2:
    I1 writes to R3 and I2 subsequently reads from R3. This is a Read After Write (RAW) dependency.
    (True)
  2. There is a WAR dependency on R3 between I1 and I3:
    I1 writes to R3 and I3 also writes to R3. This is a Write After Write (WAW) dependency, not a Write After Read (WAR) dependency.
    (False)
  3. There is a RAW dependency on R3 between I2 and I3:
    I2 reads from R3 and I3 subsequently writes to R3. This is a Write After Read (WAR) dependency, not RAW.
    (False)
  4. There is a WAW dependency on R3 between I3 and I4:
    I3 writes to R3 and I4 reads from R3. This is a Read After Write (RAW) dependency, not WAW.
    (False)

Thus, only statement A is true.

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