GATE CS 2024 Set 2 Q48 — Instruction Pipelining

To find the speedup obtained by the pipelined design over the non-pipelined design, we compare the average execution time per instruction for both designs.

1. Non-Pipelined Design

• Clock frequency ($f_{np}$) = $2\text{ GHz}$
• Average cycles per instruction ($CPI_{np}$) = $6$

Since the clock frequency is the same for both designs, we can directly work with the average clock cycles per instruction ($CPI$).

2. Pipelined Design

• Clock frequency ($f_p$) = $2\text{ GHz}$
• Ideal $CPI$ = $1$
• Data hazard stalls: $20\%$ of instructions incur an average of $2$ stall cycles.
• Control hazard stalls: $20\%$ of instructions incur an average of $3$ stall cycles.

We calculate the average $CPI$ for the pipelined design ($CPI_p$) as:

3. Speedup Calculation

Since the clock cycle time ($T_{\text{clk}}$) is identical for both configurations ($1 / 2\text{ GHz} = 0.5\text{ ns}$), the speedup is given by:

Thus, the speedup obtained by the pipelined design is 3.