GATE CS 2009 Q8 — I/O Interface: Interrupt and DMA Mode

The correct option is C.

In a standard CPU instruction cycle, the processor repeats a sequence of steps for each instruction:

1. Fetch: Retrieve the instruction from memory.
2. Decode: Determine what action the instruction requires.
3. Execute: Perform the operation.
4. Interrupt Check: Check if any interrupt requests are pending.

The CPU checks for interrupts after finishing the execution of the current instruction (and before fetching the next one) for the following reasons:

• State Consistency: It ensures that the current instruction is fully completed, leaving the CPU in a well-defined, consistent state. This makes it straightforward to save the Program Counter (PC) and processor status registers.
• Simpler Resume: When the Interrupt Service Routine (ISR) finishes, the CPU can seamlessly resume execution by simply loading the saved PC (which points to the next instruction).

Why other options are incorrect:

• Option A: Handling an interrupt immediately as soon as it is raised would stop an instruction mid-execution. Saving and restoring the precise micro-architectural state of a partially executed instruction is highly complex and inefficient.
• Option B: Checking at the end of the fetch cycle would mean interrupting the instruction after fetching but before execution, which is not standard practice for external interrupts.
• Option D: Interrupt checking is synchronized with the instruction cycle boundaries rather than arbitrary real-time clock intervals.