GATE CS 2002 Q1.9 — I/O Interface: Interrupt and DMA Mode

In microprocessors like the 8085, the interrupt handling mechanism for the INTR (Interrupt Request) line works as follows:

1. An external device requests an interrupt by raising the INTR line.
2. After completing the execution of the current instruction, the microprocessor acknowledges the request by asserting the $\overline{\text{INTA}}$ (Interrupt Acknowledge) signal active (low).
3. While $\overline{\text{INTA}}$ is active, the interrupting device is responsible for placing an instruction opcode (such as a 3-byte CALL or a 1-byte RST instruction) onto the data bus.
4. The processor reads this instruction from the data bus and executes it to branch to the appropriate Interrupt Service Routine (ISR).

Why other options are incorrect:

• HOLD: This signal is used for Direct Memory Access (DMA) requests, where an external master requests control of the system buses, not for standard device interrupts.
• READY: This signal is used to introduce wait states for slower memory or I/O devices to synchronize with the faster microprocessor, and is unrelated to the interrupt acknowledgment cycle.