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Official PYQ · 2011Q28I/O Interface: Interrupt and DMA ModeMCQ1 mark

GATE CS 2011 Q28 — I/O Interface: Interrupt and DMA Mode

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On a non-pipelined sequential processor, a program segment, which is the part of the interrupt service routine, is given to transfer 500500 bytes from an I/O device to memory.

        Initialize the address register
        Initialize the count to 500
LOOP:   Load a byte from device              
        Store in memory at address given by address register
        Increment the address register
        Decrement the count
        If count !=0 go to LOOP

Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.

The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 2020 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.

What is the approximate speed up when the DMA controller based design is used in a place of the interrupt driven program based input-output?

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Answer: A

To find the speedup of the DMA controller approach over the interrupt-driven program approach, we calculate the total clock cycles required by both methods to transfer 500500 bytes of data.

1. Interrupt-Driven Program Approach

Let's analyze the cycle requirements for each instruction based on the given rules:

  • Non-load/store instructions: Take 11 clock cycle.
  • Load/store instructions: Take 22 clock cycles.

Initialization (executed once):

  • Initialize the address register (Non-load/store): 11 cycle
  • Initialize the count to 500 (Non-load/store): 11 cycle
  • Total initialization cycles = 1+1=21 + 1 = 2 cycles

Loop Body (executed 500500 times):

  • Load a byte from device (Load): 22 cycles
  • Store in memory... (Store): 22 cycles
  • Increment the address register (Non-load/store): 11 cycle
  • Decrement the count (Non-load/store): 11 cycle
  • If count != 0 go to LOOP (Non-load/store): 11 cycle
  • Total cycles per iteration = 2+2+1+1+1=72 + 2 + 1 + 1 + 1 = 7 cycles

Total Interrupt-Driven Cycles (TinterruptT_{\text{interrupt}}):

Tinterrupt=2+(500×7)=3502 clock cyclesT_{\text{interrupt}} = 2 + (500 \times 7) = 3502 \text{ clock cycles}

2. DMA Controller Approach

  • Initialization and overheads: 2020 clock cycles
  • Data transfer: 22 clock cycles per byte for 500500 bytes

Total DMA Cycles (TDMAT_{\text{DMA}}):

TDMA=20+(500×2)=1020 clock cyclesT_{\text{DMA}} = 20 + (500 \times 2) = 1020 \text{ clock cycles}

3. Speedup Calculation

Speedup=TinterruptTDMA=35021020≈3.433\text{Speedup} = \frac{T_{\text{interrupt}}}{T_{\text{DMA}}} = \frac{3502}{1020} \approx 3.433

The approximate speedup is 3.43.4.

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