GATE CS 1998 Q1.20 — I/O Interface: Interrupt and DMA Mode

Let us analyze each option to determine the correct statement:

• Option A: Unless enabled, a CPU will not be able to process interrupts.
  This statement is true. Most interrupts are maskable. The CPU contains an Interrupt Enable (IE) flag or flip-flop. If this flag is cleared (disabled), the CPU ignores incoming maskable interrupt requests. Therefore, interrupts must be enabled for the CPU to service them.
• Option B: Loop instructions cannot be interrupted till they complete.
  This statement is false. Loops consist of multiple instructions or iterations. The CPU can be interrupted at the boundary of any instruction within the loop. Even long-running block-transfer instructions (such as REP prefix instructions in x86) can be interrupted mid-way between iterations to maintain low interrupt latency.
• Option C: A processor checks for interrupts before executing a new instruction.
  This statement is false. The processor checks for pending interrupts at the end of the execution cycle of the current instruction, rather than as a separate phase before starting a new one.
• Option D: Only level triggered interrupts are possible on microprocessors.
  This statement is false. Microprocessors support both level-triggered and edge-triggered interrupts. For example, in the 8085 microprocessor, RST 7.5 is edge-triggered, while INTR is level-triggered.

Hence, Option A is the only true statement.