GATE CS 2020 Q3 — I/O Interface: Interrupt and DMA Mode

Let us analyze each statement individually:

• Statement I: Daisy chaining is used to assign priorities in attending interrupts. (TRUE)
  Daisy chaining is a hardware-based interrupt prioritization method where devices are connected serially. The interrupt acknowledge signal propagates through the chain, meaning the device physically closest to the CPU has the highest priority and intercepts the signal first.
• Statement II: When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. (FALSE)
  In a vectored interrupt, the interrupting device itself provides the interrupt vector address (or an index) to the CPU over the data bus. The CPU uses this address directly to locate the Interrupt Service Routine (ISR), eliminating the need for polling.
• Statement III: In polling, the CPU periodically checks the status bits to know if any device needs its attention. (TRUE)
  Polling (programmed I/O) is a software-driven approach where the CPU continuously or periodically queries the status register of I/O devices to check if they are ready for data transfer.
• Statement IV: During DMA, both the CPU and DMA controller can be bus masters at the same time. (FALSE)
  The system bus can have only one bus master at any given instant to prevent bus contention and data collision. During DMA transfer, the CPU relinquishes control of the buses, and the DMA controller becomes the sole bus master.

Therefore, only statements I and III are TRUE.