GATE CS Computer Organization and Architecture questions

Practise Computer Organization and Architecture questions for GATE CS. Explore official PYQs and original subject-wise quizzes, check answers and view available solutions. Free, no sign-in.

Track address sizes, cache organisation and pipeline dependencies carefully. Write down the units and assumptions before computing memory access times or processor performance.

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SubjectTopicYearType

A cache memory that has a hit rate of

0.8

has an access latency

10 \; \text{ns}

and miss penalty

100 \; \text{ns}.

An optimization is done on the cache to reduce the miss rate. However, the optimization results in an increase of cache access latency to

15 \; \text{ns},

whereas the miss penalty is not affected. The minimum hit rate (rounded …

Consider a system with

2 \;\text{KB}

direct mapped data cache with a block size of

64 \; \text{bytes}.

The system has a physical address space of

64 \; \text{KB}

and a word length of

16 \; \text{bits.}

During the execution of a program, four data words

\text{P, Q, R,}

\text{S}

are accessed in that order

10

\text{X}_{1}

2 \; \text{GHz}

5-

\text{RISC}

instruction pipeline having a base

\text{CPI (cycles per instruction)}

of one without any pipeline hazards. For a given program

\text{P}

30 \%

branch instructions, control hazards incur

2

cycles stall for every branch. A new …

Consider a computer system with a byte-addressable primary memory of size

2^{32}

bytes. Assume the computer system has a direct-mapped cache of size

\text{32 KB}

\text{1 KB}

2^{10}

bytes), and each cache block is of size

64

bytes. The size of the tag field is __________ bits.

A five-stage pipeline has stage delays of

150, 120, 150, 160

140

nanoseconds. The registers that are used between the pipeline stages have a delay of

5

nanoseconds each. The total time to execute

100

independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.

Consider the following instruction sequence where registers

\text{R1}, \text{R2}

\text{R3}

are general purpose and

\text{MEMORY[X]}

denotes the content at the memory location

\text{X}.

Consider a set-associative cache of size

\text{2KB (1KB} =2^{10}

\text{)}

with cache block size of

64

bytes. Assume that the cache is byte-addressable and a

32

-bit address is used for accessing the cache. If the width of the tag field is

22

bits, the associativity of the cache is _________

Consider a computer system with

\text{DMA}

\text{DMA}

module is transferring one

8

-bit character in one

\text{CPU}

cycle from a device to memory through cycle stealing at regular intervals. Consider a

\text{2 MHz}

0.5 \%

processor cycles are used for

\text{DMA}

, the data transfer rate of the device is …

Assume a two-level inclusive cache hierarchy,

L1

L2

L2

is the larger of the two. Consider the following statements.

S_1

: Read misses in a write through

L1

cache do not result in writebacks of dirty lines to the

L2

S_2

: Write allocate policy must be used in conjunction with write through caches and no-write …

Consider a pipelined processor with

5

\text{Instruction Fetch} (\textsf{IF})

\text{Instruction Decode} \textsf{(ID)}

\text{Execute } \textsf{(EX)}

\text{Memory Access } \textsf{(MEM)}

\text{Write Back } \textsf{(WB)}

. Each stage of the pipeline, except the

\textsf{EX}

stage, takes one cycle. Assume that the …

Consider the following statements. Daisy chaining is used to assign priorities in attending interrupts. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. In polling, the CPU periodically checks the status bits to know if any device needs its attention. During DMA, both the CPU and DMA controller can be bus …

Consider the following data path diagram. Consider an instruction:

R0 \leftarrow R1 +R2

. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts

r

w

indicate read and write operations, respectively.

R2_{r},\text{ TEMP1}_{r},ALU_{\text{add}}, \text{ TEMP2}_{w}

A direct mapped cache memory of

1

MB has a block size of

256

bytes. The cache has an access time of

3

ns and a hit rate of

94 \%

. During a cache miss, it takes

2

0 ns to bring the first word of a block from the main memory, while each subsequent word takes

5

ns. The word size is

64

bits. The average memory access time in ns (round …

A computer system with a word length of

32

16

MB byte- addressable main memory and a

64

4

-way set associative cache memory with a block size of

256

bytes. Consider the following four physical addresses represented in hexadecimal notation.

A1= \textsf{0x42C8A4}

A2= \textsf{0x546888}

A3= \textsf{0x6A289C}

Consider a non-pipelined processor operating at

2.5

5

clock cycles to complete an instruction. You are going to make a

5

- stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at

2

GHz. In a given program, assume that

30\%

are memory instructions,

60 \%

A processor has

64

registers and uses

16

-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a

4

-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are

8

distinct I-type opcodes, then the maximum number of …

A certain processor uses a fully associative cache of size

16

kB, The cache block size is

16

bytes. Assume that the main memory is byte addressable and uses a

32

-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?

The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has

16

address lines denoted by

A_{15}

A_0

. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

A certain processor deploys a single-level cache. The cache block size is

8

words and the word size is

4

bytes. The memory system uses a

60

-MHz clock. To service a cache miss, the memory controller first takes

1

cycle to accept the starting address of the block, it then takes

3

cycles to fetch all the eight words of the block, and finally …

A processor has

16

integer registers

\text{(R0, R1}, \ldots ,\text{ R15)}

64

floating point registers

\text{(F0, F1}, \ldots , \text{F63)}.

2\text{- byte}

instruction format. There are four categories of instructions:

\text{Type-1, Type-2, Type-3},

\text{Type-4. Type-1}

category consists of four instructions, …