GATE CS 2020 Q43 — Instruction Pipelining

To find the speedup achieved by the pipelined processor over the non-pipelined processor, we compare the average execution time per instruction for both cases.

1. Non-Pipelined Processor

• Frequency ($f_{\text{np}}$): $2.5\text{ GHz}$
• Clock cycle time ($t_{\text{np}}$): $\frac{1}{2.5\text{ GHz}} = 0.4\text{ ns}$
• Cycles per instruction ($CPI_{\text{np}}$): $5$

Average execution time per instruction ($T_{\text{np}}$):

2. Pipelined Processor

• Frequency ($f_{\text{p}}$): $2\text{ GHz}$
• Clock cycle time ($t_{\text{p}}$): $\frac{1}{2\text{ GHz}} = 0.5\text{ ns}$
• Ideal CPI: $1$

Instruction Mix and Stalls:

• Memory Instructions ($30\%$ of total):

  $5\%$ of these cause $50$ stall cycles each.

  $$\text{Average memory stalls per instruction} = 0.30 \times 0.05 \times 50 = 0.75\text{ cycles}$$
• Branch Instructions ($10\%$ of total, since $100\% - 30\% - 60\% = 10\%$):

  $50\%$ of these cause $2$ stall cycles each.

  $$\text{Average branch stalls per instruction} = 0.10 \times 0.50 \times 2 = 0.10\text{ cycles}$$
• ALU Instructions ($60\%$ of total):

  These cause $0$ stalls.

Average CPI of the Pipelined Processor ($CPI_{\text{p}}$):

Average execution time per instruction ($T_{\text{p}}$):

3. Speedup Calculation

Rounding off to two decimal places, the speedup is 2.16.