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Official PYQ · 2019Q45Memory Hierarchy: Cache, Main Memory and Secondary StorageNAT2 marks

GATE CS 2019 Q45 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

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A certain processor deploys a single-level cache. The cache block size is 88 words and the word size is 44 bytes. The memory system uses a 6060-MHz clock. To service a cache miss, the memory controller first takes 11 cycle to accept the starting address of the block, it then takes 33 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 11 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is  ______×106\times 10^6 bytes/sec.
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Answer: 160

To find the maximum bandwidth of the memory system, we calculate the total clock cycles required to transfer one cache block during a series of read operations.

1. Block Size in Bytes:
Block size=8 words×4 bytes/word=32 bytes\text{Block size} = 8 \text{ words} \times 4 \text{ bytes/word} = 32 \text{ bytes}

2. Total Clock Cycles per Block Transfer:

  • Accepting starting address: 11 cycle
  • Fetching the block: 33 cycles
  • Transmitting 88 words (11 cycle per word): 88 cycles
Total cycles=1+3+8=12 cycles\text{Total cycles} = 1 + 3 + 8 = 12 \text{ cycles}

3. Maximum Bandwidth:
Given the clock frequency is 60 MHz60\text{ MHz}, the bandwidth is:
Bandwidth=32 bytes12 cycles×60×106 cycles/sec=160×106 bytes/sec\text{Bandwidth} = \frac{32 \text{ bytes}}{12 \text{ cycles}} \times 60 \times 10^6 \text{ cycles/sec} = 160 \times 10^6 \text{ bytes/sec}

Thus, the maximum bandwidth is 160.

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