GATE CS Memory Hierarchy: Cache, Main Memory and Secondary Storage questions

The size of the physical address space of a processor is $2^{32}$ bytes. The capacity of a cache memory unit is $2^{23}$ bytes. The cache block size is $128$ bytes. The cache memory unit can be built as a direct mapped cache or as a $K$-way set-associative cache, where $K=2^{L}$ and $L \in\{1,2,3\}$. Let the length of the TAG field be $M$ bits …

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid. For a given memory reference, which of the …

Consider a hard disk with a rotational speed of $15000$ rpm. The time to move the read/write head from a track to its adjacent track is $1$ millisecond. Initially, the head is on track $0$. The number of sectors per track is $400$. The sector size is $1024$ bytes. It is necessary to transfer data from $10$ randomly located sectors in each of the …

Consider a system with a processor and a $4$ KB direct mapped cache with block size of $16$ bytes. The system has a $16$ MB physical memory. Four words $\mathrm{P}, \mathrm{Q}, \mathrm{R}$, and S are accessed by the processor in the same order $10$ times. That is, there are a total of $40$ memory references in the sequence …

To keep track of free blocks in a file system, one of the two approaches is generally used - using bitmaps (bit vectors) or using linked lists. Consider that the linked list approach is used to keep track of free blocks in a file system. Assume that the disk size is $16$ GB , block size is $2$ KB , and block numbers used are $32$-bit long. A single …

Consider a system with $1$ MB physical memory and a word length of $1$ byte. The system uses a direct mapped cache, with block numbers starting from $0$. The word with physical address $\text{0xA2C28}$ is mapped to the cache block number $17610$. The maximum possible size of the cache (in KB ) for this configuration is $\_\_\_\_\_\_\_$. (answer …

Consider a memory system with $1 \mathrm{M}$ bytes of main memory and $16 \mathrm{~K}$ bytes of cache memory. Assume that the processor generates $20$-bit memory address, and the cache block size is $16$ bytes. If the cache uses direct mapping, how many bits will be required to store all the $\operatorname{tag}$ values? [Assume memory is byte …

A computer has a memory hierarchy consisting of two-level cache $\text{(L1}$ and $\text{L2)}$ and a main memory. If the processor needs to access data from memory, it first looks into $\text{L1}$ cache. If the data is not found in $\text{L1}$ cache, it goes to $\text{L2}$ cache. If it fails to get the data from $\text{L2}$ cache, it goes to main …

Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is $1$ nanosecond (ns) and the "hit rate" for L1 cache is $90 \%$ while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the "hit rate" is $80 \%$ and the "miss penalty" for transferring …

​​​​For a direct-mapped cache, $4$ bits are used for the tag field and $12$ bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no other information stored for each cache block. Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte …

​​​​Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write through policy. Both of them use the $\text{LRU}$ (Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?

A given program has $25 \%$ load/store instructions. Suppose the ideal $\text{CPI}$ (cycles per instruction) without any memory stalls is $2$. The program exhibits $2 \%$ miss rate on instruction cache and $8 \%$ miss rate on data cache. The miss penalty is $100$ cycles. The speedup (rounded off to two decimal places) achieved with a perfect …

The baseline execution time of a program on a $2 \mathrm{GHz}$ single core machine is $100$ nanoseconds ( $n s)$. The code corresponding to $90 \%$ of the execution time can be fully parallelized. The overhead for using an additional core is $10 ~ns$ when running on a multicore system. Assume that all cores in the multicore system run their share …

A $4$ kilobyte $\text{(KB)}$ byte-addressable memory is realized using four $1 \mathrm{~KB}$ memory blocks. Two input address lines $\text{(IA4 and IA3)}$ are connected to the chip select $\text{(CS)}$ port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from $\text{IA11-IA0}$ are connected …

An $8$-way set associative cache of size $64 \mathrm{~KB} \;(1 \mathrm{~KB}=1024\; \text{bytes})$ is used in a system with $32$-bit address. The address is sub-divided into $\text{TAG, INDEX},$ and $\text{BLOCK OFFSET.}$ The number of bits in the $\text{TAG}$ is ___________.

Let $\text{WB}$ and $\text{WT}$ be two set associative cache organizations that use $\text{LRU}$ algorithm for cache block replacement. $\text{WB}$ is a write back cache and $\text{WT}$ is a write through cache. Which of the following statements is/are $\text{FALSE}?$

A cache memory that has a hit rate of $0.8$ has an access latency $10 \; \text{ns}$ and miss penalty $100 \; \text{ns}.$ An optimization is done on the cache to reduce the miss rate. However, the optimization results in an increase of cache access latency to $15 \; \text{ns},$ whereas the miss penalty is not affected. The minimum hit rate (rounded …

Consider a system with $2 \;\text{KB}$ direct mapped data cache with a block size of $64 \; \text{bytes}.$ The system has a physical address space of $64 \; \text{KB}$ and a word length of $16 \; \text{bits.}$ During the execution of a program, four data words $\text{P, Q, R,}$ and $\text{S}$ are accessed in that order $10$ times …

Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.

Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________