GATE CS 2023 Q32 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

The system has a total of 12 address lines, $\text{IA11}$ to $\text{IA0}$. Out of these, two address lines $\text{IA4}$ and $\text{IA3}$ are used as inputs to the $2 \times 4$ decoder to select one of the four $1\text{ KB}$ memory blocks ($X_1, X_2, X_3, X_4$).

The remaining 10 address lines ($\text{IA11-IA5}$ and $\text{IA2-IA0}$) are connected to the address ports of the memory blocks. For the starting location ($\text{Addr} = 0$) of any block, all these 10 internal address lines must be set to $0$:

The starting address of each block is determined solely by the selection lines $(\text{IA4}, \text{IA3})$:

• Block $X_1$ $(\text{IA4}\ \text{IA3} = 00_2)$: Address $= 000000000000_2 = 0$
• Block $X_2$ $(\text{IA4}\ \text{IA3} = 01_2)$: Address $= 000000001000_2 = 8$
• Block $X_3$ $(\text{IA4}\ \text{IA3} = 10_2)$: Address $= 000000010000_2 = 16$
• Block $X_4$ $(\text{IA4}\ \text{IA3} = 11_2)$: Address $= 000000011000_2 = 24$

Thus, the starting decimal addresses of the blocks are $(0, 8, 16, 24)$.