Consider a system with direct mapped data cache with a block size of The system has a physical address space of and a word length of During the execution of a program, four data words and are accessed in that order times Hence, there are accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of and are and respectively. For the execution of the above program, which of the following statements is/are with respect to the data cache?
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Answer: A;B;D
To analyze the cache behavior, we first determine the address division for the direct-mapped cache:
- Cache Size:
- Block Size: Block Offset:
- Number of Cache Lines: Line Index:
- Tag Size:
Now, we convert the physical addresses of the first bytes of and to binary to find their Tag (bits 15–11) and Line Index (bits 10–6):
- P (0xA248):
10100 01001 001000Tag = , Line Index = - Q (0xC28A):
11000 01010 001010Tag = , Line Index = - R (0xCA8A):
11001 01010 001010Tag = , Line Index = - S (0xA262):
10100 01001 100010Tag = , Line Index =
From this mapping, we observe:
- P and S have the same Tag () and Line Index (). Thus, they reside in the same cache block on Line 9.
- Q and R map to the same Line Index () but have different Tags ( and ). Thus, they conflict and evict each other.
Let's evaluate the statements based on the access sequence :
- Statement A is TRUE: The very first access to loads the block containing both and into Line 9. Since Line 9 is never evicted, every subsequent access to is a hit.
- Statement B is TRUE: No other accessed data maps to Line 9, so once is loaded, it is never evicted.
- Statement C is FALSE: At the end of execution, the block containing and remains in Line 9, and the block containing is in Line 10. Thus, , , and all reside in the cache.
- Statement D is TRUE: Since is accessed immediately before in each iteration, is always in Line 10 when is accessed. Thus, every access to evicts .
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