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GATE CS 2022 Q44 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

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Consider a system with 2  KB2 \;\text{KB} direct mapped data cache with a block size of 64  bytes.64 \; \text{bytes}. The system has a physical address space of 64  KB64 \; \text{KB} and a word length of 16  bits.16 \; \text{bits.} During the execution of a program, four data words P, Q, R,\text{P, Q, R,} and S\text{S} are accessed in that order 1010 times (i.e., PQRSPQRS… ).\text{(i.e., PQRSPQRS}\dots). Hence, there are 4040 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R,\text{P, Q, R,} and S\text{S} are 0xA248, 0xC28A, 0xCA8A,\text{0xA248, 0xC28A, 0xCA8A,} and 0xA262,\text{0xA262}, respectively. For the execution of the above program, which of the following statements is/are TRUE\text{TRUE} with respect to the data cache?

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Answer: A;B;D

To analyze the cache behavior, we first determine the address division for the direct-mapped cache:

  • Cache Size: 2 KB=211 bytes2 \text{ KB} = 2^{11} \text{ bytes}
  • Block Size: 64 bytes=26 bytes  ⟹  64 \text{ bytes} = 2^6 \text{ bytes} \implies Block Offset: 6 bits6 \text{ bits}
  • Number of Cache Lines: 2 KB64 bytes=32=25  ⟹  \frac{2 \text{ KB}}{64 \text{ bytes}} = 32 = 2^5 \implies Line Index: 5 bits5 \text{ bits}
  • Tag Size: 16−(5+6)=5 bits16 - (5 + 6) = 5 \text{ bits}

Now, we convert the physical addresses of the first bytes of P, Q, R,\text{P, Q, R,} and S\text{S} to binary to find their Tag (bits 15–11) and Line Index (bits 10–6):

  • P (0xA248): 10100 01001 001000   ⟹  \implies Tag = 2020, Line Index = 99
  • Q (0xC28A): 11000 01010 001010   ⟹  \implies Tag = 2424, Line Index = 1010
  • R (0xCA8A): 11001 01010 001010   ⟹  \implies Tag = 2525, Line Index = 1010
  • S (0xA262): 10100 01001 100010   ⟹  \implies Tag = 2020, Line Index = 99

From this mapping, we observe:

  1. P and S have the same Tag (2020) and Line Index (99). Thus, they reside in the same cache block on Line 9.
  2. Q and R map to the same Line Index (1010) but have different Tags (2424 and 2525). Thus, they conflict and evict each other.

Let's evaluate the statements based on the access sequence P→Q→R→S\text{P} \to \text{Q} \to \text{R} \to \text{S}:

  • Statement A is TRUE: The very first access to P\text{P} loads the block containing both P\text{P} and S\text{S} into Line 9. Since Line 9 is never evicted, every subsequent access to S\text{S} is a hit.
  • Statement B is TRUE: No other accessed data maps to Line 9, so once P\text{P} is loaded, it is never evicted.
  • Statement C is FALSE: At the end of execution, the block containing P\text{P} and S\text{S} remains in Line 9, and the block containing R\text{R} is in Line 10. Thus, P\text{P}, R\text{R}, and S\text{S} all reside in the cache.
  • Statement D is TRUE: Since Q\text{Q} is accessed immediately before R\text{R} in each iteration, Q\text{Q} is always in Line 10 when R\text{R} is accessed. Thus, every access to R\text{R} evicts Q\text{Q}.

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