GATE CS 2019 Q2 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

To find the enabled address range, we analyze the logic gates that generate the active-low chip select signal $\overline{\text{CS}}$:

• An AND gate with inputs $A_{15}$ and $A_{14}$ produces the output $A_{15} \cdot A_{14}$.
• A NOR gate with inputs $A_{13}$ and $A_{12}$ produces the output $\overline{A_{13} + A_{12}}$.
• A 3-input NAND gate takes these two outputs along with $A_{11}$ to produce the active-low chip select signal:$$\overline{\text{CS}} = \overline{(A_{15} \cdot A_{14}) \cdot (\overline{A_{13} + A_{12}}) \cdot A_{11}}$$

For the DRAM chip to be enabled, we require $\overline{\text{CS}} = 0$. This is achieved when all inputs to the final NAND gate are $1$:

1. $A_{15} \cdot A_{14} = 1 \implies A_{15} = 1$ and $A_{14} = 1$
2. $\overline{A_{13} + A_{12}} = 1 \implies A_{13} = 0$ and $A_{12} = 0$
3. $A_{11} = 1$

Thus, the upper 5 address bits are fixed as $A_{15}A_{14}A_{13}A_{12}A_{11} = 11001_2$. The remaining 11 bits ($A_{10}$ to $A_0$) can vary freely from all $0$s to all $1$s:

• Minimum Address: $1100\;1000\;0000\;0000_2 = \text{C800}_{16}$
• Maximum Address: $1100\;1111\;1111\;1111_2 = \text{CFFF}_{16}$

Therefore, the address range is C800 to CFFF.