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GATE CS 2019 Q1 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

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A certain processor uses a fully associative cache of size 1616 kB, The cache block size is 1616 bytes. Assume that the main memory is byte addressable and uses a 3232-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?

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Answer: D

In a fully associative cache, any main memory block can be placed in any cache line. Therefore, no index bits are required to select a specific cache set or line.

The physical address is divided into two fields:

  • Block Offset: Determined by the block size. Since the block size is 1616 bytes (242^4 bytes), the block offset requires log⁡2(16)=4\log_2(16) = 4 bits.
  • Tag: The remaining bits of the address. Since the address is 3232 bits, the Tag field requires 32−4=2832 - 4 = 28 bits.

Thus, the number of bits for the Tag and Index fields are 2828 bits and 00 bits respectively.

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