GATE CS Computer Organization and Architecture questions

Practise Computer Organization and Architecture questions for GATE CS. Explore official PYQs and original subject-wise quizzes, check answers and view available solutions. Free, no sign-in.

Track address sizes, cache organisation and pipeline dependencies carefully. Write down the units and assumptions before computing memory access times or processor performance.

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SubjectTopicYearType

3 \ \text{GHz}

(gigahertz) processor with a three stage pipeline and stage latencies

\large\tau_1,\tau_2

\large\tau_3

\large\tau_1 =\dfrac{3 \tau_2}{4}=2\tau_3

. If the longest pipeline stage is split into two pipeline stages of equal latency , the new frequency is __________

\text{GHz}

, ignoring delays in the …

A processor has

40

distinct instruction and

24

general purpose registers. A

32

-bit instruction word has an opcode, two registers operands and an immediate operand. The number of bits available for the immediate operand field is_______.

Consider a non-pipelined processor with a clock rate of

2.5

gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to

2

gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this …

Consider the sequence of machine instruction given below:

\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} & \text{R6, R2, R3} \\ \text{ADD} & \text{R7, R5, R6} \\ \text{SUB} & \text{R8, R7, R4} \\ \end{array}

In the above sequence,

R0

R8

are general purpose registers. In the instructions shown, the first register …

Consider a processor with byte-addressable memory. Assume that all registers, including program counter (PC) and Program Status Word (PSW), are size of two bytes. A stack in the main memory is implemented from memory location

(0100)_{16}

and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is …

Assume that for a certain processor, a read request takes

50\:\text{nanoseconds}

on a cache miss and

5\:\text{nanoseconds}

on a cache hit. Suppose while running a program, it was observed that

80\%

of the processor's read requests result in a cache hit. The average read access time in nanoseconds is ______.

Consider the following reservation table for a pipeline having three stages

S_1, S_2 \text{ and } S_3

Consider the following code sequence having five instructions from

I_1 \text{ to } I_5

. Each of these instructions has the following format. OP Ri, Rj, Rk Where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri.

I_1

: ADD R1, R2, R3

I_2

: MUL R7, R1, R3

I_3

: SUB R4, R1, R5

I_4

: ADD R3, R2, …

Consider a machine with a byte addressable main memory of

2^{20}

bytes, block size of

16

bytes and a direct mapped cache having

2^{12}

cache lines. Let the addresses of two consecutive bytes in main memory be

\textsf{(E201F)}_{16}

\textsf{(E2020)}_{16}

. What are the tag and cache line addresses ( in hex) for main memory address …

Consider two processors

P_1

P_2

executing the same instruction set. Assume that under identical conditions, for the same input, a program running on

P_2

\text{25\%}

less time but incurs

\text{20\%}

more CPI (clock cycles per instruction) as compared to the program running on

P_1

. If the clock frequency of

P_1

An access sequence of cache block addresses is of length

N

and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by

k

. What is the miss ratio if the access sequence is passed through a cache of associativity

A\geq k

exercising least-recently-used …

6

-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this

6

-stage pipeline, the speedup achieved with respect to non-pipelined execution if

25

% of the instructions incur

2

pipeline stall cycles is ____________

A machine has a

32\text{-bit}

architecture, with

1\text{-word}

long instructions. It has

64

registers, each of which is

32

bits long. It needs to support

45

instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate …

If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?

In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?

4

-way set-associative cache memory unit with a capacity of

16

KB is built using a block size of

8

words. The word length is

32

bits. The size of the physical address space is

4

GB. The number of bits for the TAG field is ____

The memory access time is

1

nanosecond for a read operation with a hit in cache,

5

nanoseconds for a read operation with a miss in cache,

2

nanoseconds for a write operation with a hit in cache and

10

nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves

100

instruction fetch operations, …

An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies

1

2.2

2

1

0.75

ns, respectively (ns stands for nanoseconds). To gain in terms of frequency, the …

Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.

\text{P1:}

Four-stage pipeline with stage latencies

\text{1 ns, 2 ns, 2 ns, 1 ns}

\text{P2:}

Four-stage pipeline with stage latencies

\text{1 ns, 1.5 ns, 1.5 ns, 1.5 ns}

\text{P3:}

Five-stage pipeline with stage latencies …

Consider the following sequence of micro-operations. MBR ← PC MAR ← X PC ← Y Memory ← MBR Which one of the following is a possible operation performed by this sequence?