GATE CS 2014 Set 1 Q43 — Instruction Pipelining

To find the speedup achieved by the pipelined processor over the non-pipelined processor, we use the standard speedup formula for a large number of instructions:

Given:

• Number of pipeline stages ($k$) = $6$
• The stages are perfectly balanced with no pipelining overhead. Therefore, if the clock cycle time of the pipelined processor is $\tau$, the clock cycle time of the non-pipelined processor is $6\tau$.
• For a non-pipelined processor, each instruction takes $1$ clock cycle of duration $6\tau$ (or $6$ cycles of duration $\tau$). Thus, $\text{CPI}_{\text{non-pipelined}} = 1$ with cycle time $6\tau$.

For the pipelined processor:

• The ideal $\text{CPI}_{\text{pipelined}}$ is $1$.
• $25\%$ of the instructions incur $2$ stall cycles.
• Average stall cycles per instruction = $0.25 \times 2 = 0.5$ cycles.
• Actual $\text{CPI}_{\text{pipelined}} = \text{Ideal CPI} + \text{Average Stall Cycles} = 1 + 0.5 = 1.5$.

Substituting these values into the speedup formula:

Thus, the speedup achieved is 4.