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Official PYQ · 2014

GATE CS 2014 Set 1 Q44 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

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An access sequence of cache block addresses is of length NN and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by kk. What is the miss ratio if the access sequence is passed through a cache of associativity A≥kA\geq k exercising least-recently-used replacement policy?

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Answer: A

To find the miss ratio, let us analyze the behavior of the Least-Recently-Used (LRU) replacement policy under the given conditions:

  1. Total Accesses and Unique Blocks: The total number of accesses in the sequence is NN, and there are nn unique block addresses.
  2. LRU Cache Behavior: Under the LRU policy, a block is evicted from a cache of associativity (or capacity) AA only if at least AA other unique blocks are accessed after its most recent access.
  3. No Capacity/Conflict Misses: We are given that the number of unique block addresses accessed between any two consecutive accesses to the same block is bounded above by kk. Since the cache associativity is A≥kA \geq k, the block will never be evicted from the cache before it is accessed again. Thus, every subsequent access to an already-loaded block is guaranteed to be a cache hit.
  4. Compulsory Misses: Since no block is ever evicted once loaded, the only misses that occur are the very first accesses to each of the nn unique blocks. These are called compulsory (or cold) misses. Therefore, the total number of cache misses is exactly nn.

The miss ratio is defined as:

Miss Ratio=Total MissesTotal Accesses=nN\text{Miss Ratio} = \frac{\text{Total Misses}}{\text{Total Accesses}} = \frac{n}{N}

Hence, the correct option is A.

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