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Official PYQ · 2015

GATE CS 2015 Set 1 Q38 — Instruction Pipelining

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Consider a non-pipelined processor with a clock rate of 2.52.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 22 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is_______________.
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Answer: 3.2

To find the speedup achieved by the pipelined processor, we compare the average execution time per instruction for both the non-pipelined and pipelined processors.

1. Non-Pipelined Processor

  • Clock rate (fnon-pipef_{\text{non-pipe}}): 2.5 GHz2.5\text{ GHz}
  • Clock cycle time (Tnon-pipeT_{\text{non-pipe}}): 12.5 GHz=0.4 ns\frac{1}{2.5\text{ GHz}} = 0.4\text{ ns}
  • Cycles Per Instruction (CPInon-pipe\text{CPI}_{\text{non-pipe}}): 44

Average execution time per instruction (ETnon-pipe\text{ET}_{\text{non-pipe}}):

ETnon-pipe=CPInon-pipe×Tnon-pipe=4×0.4 ns=1.6 ns\text{ET}_{\text{non-pipe}} = \text{CPI}_{\text{non-pipe}} \times T_{\text{non-pipe}} = 4 \times 0.4\text{ ns} = 1.6\text{ ns}

2. Pipelined Processor

  • Clock rate (fpipef_{\text{pipe}}): 2 GHz2\text{ GHz}
  • Clock cycle time (TpipeT_{\text{pipe}}): 12 GHz=0.5 ns\frac{1}{2\text{ GHz}} = 0.5\text{ ns}
  • Cycles Per Instruction (CPIpipe\text{CPI}_{\text{pipe}}): Since there are no stalls in the pipeline, the ideal CPI in the steady state is 11.

Average execution time per instruction in steady state (ETpipe\text{ET}_{\text{pipe}}):

ETpipe=CPIpipe×Tpipe=1×0.5 ns=0.5 ns\text{ET}_{\text{pipe}} = \text{CPI}_{\text{pipe}} \times T_{\text{pipe}} = 1 \times 0.5\text{ ns} = 0.5\text{ ns}

3. Speedup

The speedup (SS) is given by the ratio of the execution times:

S=ETnon-pipeETpipe=1.6 ns0.5 ns=3.2S = \frac{\text{ET}_{\text{non-pipe}}}{\text{ET}_{\text{pipe}}} = \frac{1.6\text{ ns}}{0.5\text{ ns}} = 3.2

Thus, the speedup achieved is 3.2.

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