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Official PYQ · 2014

GATE CS 2014 Set 2 Q43 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

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In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?

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Answer: D

To determine the correct statement, let us analyze each option in the context of cache design parameters:

  • Option A (Incorrect): Spatial locality states that if a memory location is accessed, nearby locations are likely to be accessed soon. A larger block size brings more neighboring data into the cache on a miss, thereby exploiting spatial locality better. A smaller block size reduces this advantage.
  • Options B & C (Incorrect): Let the cache size be CC, block size be BB, and associativity be KK.
    • The number of sets is S=CB×KS = \frac{C}{B \times K}.
    • The number of index bits is s=log⁡2(S)=log⁡2(CK)−log⁡2(B)s = \log_2(S) = \log_2\left(\frac{C}{K}\right) - \log_2(B).
    • The number of offset bits is b=log⁡2(B)b = \log_2(B).
    • The tag size per line is: Tag bits=Address bits−s−b=Address bits−log⁡2(CK)\text{Tag bits} = \text{Address bits} - s - b = \text{Address bits} - \log_2\left(\frac{C}{K}\right) This shows that the tag size per cache line is independent of the block size BB.
    • However, because the block size BB is smaller, the number of cache lines (N=C/BN = C/B) increases. Consequently, the total tag overhead (total tag bits across all lines) increases. Thus, B and C are incorrect.
  • Option D (Correct): The cache miss penalty is the time required to bring a block from the main memory to the cache. This time consists of the memory latency (access time) plus the transfer time. Since the transfer time is directly proportional to the block size, a smaller block size requires transferring fewer bytes, which results in a lower cache miss penalty.

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