The clock cycle time of a pipeline is determined by the latency of its longest stage. Let the stage latencies be τ1,τ2, and τ3. We are given the relationship:
τ1=43τ2=2τ3
Expressing all stage latencies in terms of τ1:
- τ1=τ1
- τ2=34τ1≈1.33τ1
- τ3=21τ1=0.5τ1
Comparing the values, the longest stage is τ2. Therefore, the clock cycle time of the original pipeline is:
T=τ2
Given that the original frequency is 3 GHz, the clock cycle time T is:
T=τ2=31 ns
Using this, we can find the latency of the other stages:
τ1=43τ2=43×31=41 ns
τ3=21τ1=21×41=81 ns
The longest stage (τ2) is split into two pipeline stages of equal latency. The latency of each of these new stages is:
τ2a=τ2b=2τ2=21/3=61 ns
The latencies of the four stages in the new pipeline are:
τ1=41 ns,τ2a=61 ns,τ2b=61 ns,τ3=81 ns
The new clock cycle time T′ is determined by the maximum latency among the new stages:
T′=max(41,61,61,81)=41 ns
Thus, the new frequency f′ is:
f′=T′1=1/4 ns1=4 GHz