GATE CS 2014 Set 3 Q43 — Instruction Pipelining

To find the ratio of the execution times $P/Q$, we first determine the clock cycle times and average CPIs for both pipeline designs.

• Old Design: The clock cycle time is determined by the slowest stage latency: $$t_{\text{old}} = \max(1, 2.2, 2, 1, 0.75) = 2.2 \text{ ns}$$
• New Design: The ID/RF stage is split into three stages (each $2.2/3 \approx 0.733$ ns) and the EX stage into two stages (each $1$ ns). The clock cycle time is: $$t_{\text{new}} = \max\left(1, \frac{2.2}{3}, 1, 1, 1, 0.75\right) = 1 \text{ ns}$$

• For non-branch instructions ($80\%$ of the program), average $\text{CPI} = 1$ in both designs.
• For branch instructions ($20\%$ of the program):
  • Old Design: The target address is available at the end of the EX stage (3rd stage: IF, ID/RF, EX). This causes $2$ stall cycles, so $\text{CPI}_{\text{branch}} = 1 + 2 = 3$.
  • New Design: The target address is available at the end of the EX2 stage (6th stage: IF, ID, RF1, RF2, EX1, EX2). This causes $5$ stall cycles, so $\text{CPI}_{\text{branch}} = 1 + 5 = 6$.

Now, we compute the average CPI for both designs:

Let $N$ be the total number of instructions:

The value $1.54$ lies within the range of 1.50 : 1.60.