Official PYQ · 2015Set 2 · Q44Instruction PipeliningNAT1 mark

GATE CS 2015 Set 2 Q44 — Instruction Pipelining

Consider the sequence of machine instruction given below:

\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} & \text{R6, R2, R3} \\ \text{ADD} & \text{R7, R5, R6} \\ \text{SUB} & \text{R8, R7, R4} \\ \end{array}

In the above sequence,

R0

R8

are general purpose registers. In the instructions shown, the first register shows the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following

4

stages:

(1)

Instruction Fetch and Decode

(IF)

(2)

Operand Fetch

(OF)

(3)

Perform Operation

(PO)

and

(4)

Write back the result

(WB)

. The

IF

OF

and

WB

stages take

1

clock cycle each for any instruction. The

PO

stage takes

1

clock cycle for ADD and SUB instruction,

3

clock cycles for MUL instruction and

5

clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instruction is _________.

View worked solution

Answer: 13

To find the total number of clock cycles, we trace the execution of each instruction through the pipeline stages: IF (Instruction Fetch), OF (Operand Fetch), PO (Perform Operation), and WB (Write Back).

Since operand forwarding is available from the PO stage to the OF stage, a dependent instruction can perform its OF stage in the cycle immediately following the completion of the source instruction's PO stage.

The cycle-by-cycle execution is shown in the table below:

Instruction	1	2	3	4	5	6	7	8	9	10	11	12	13
I1: MUL R5, R0, R1	IF	OF	PO	PO	PO	WB
I2: DIV R6, R2, R3		IF	OF	PO	PO	PO	PO	PO	WB
I3: ADD R7, R5, R6			IF	stall	stall	stall	stall	stall	OF	PO	WB
I4: SUB R8, R7, R4				IF	stall	stall	stall	stall	stall	stall	OF	PO	WB

Key Details:

I3 (ADD) depends on $R5$ (from I1) and $R6$ (from I2). $R5$ is ready at the end of cycle 5, and $R6$ is ready at the end of cycle 8. Thus, the OF of I3 must wait until cycle 9.
I4 (SUB) depends on $R7$ (from I3). $R7$ is ready at the end of cycle 10. Thus, the OF of I4 must wait until cycle 11.

The entire sequence completes execution at the end of 13 clock cycles.

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Published 10 Oct 2026

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