GATE CS 2014 Set 2 Q44 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

Let us analyze how changing the cache associativity affects each parameter. Let:

• $C$ = Cache capacity
• $B$ = Block size
• $P$ = Associativity (number of blocks per set)

The number of sets in the cache is given by:

When the associativity $P$ is doubled ($P' = 2P$) while keeping capacity $C$ and block size $B$ constant:

1. Number of sets ($S$): It is halved ($S' = S/2$). Therefore, the number of set index bits decreases by $1$ (since $\log_2(S') = \log_2(S) - 1$). This directly changes the width of the set index decoder (Option B is affected).
2. Tag bits: Since the set index bits decrease by $1$ and the block offset bits remain unchanged, the number of tag bits must increase by $1$ to maintain the same physical address width. This changes the width of the tag comparator (Option A is affected).
3. Way selection multiplexer: The multiplexer must select $1$ out of $P$ ways. Since associativity $P$ is doubled, the size of this multiplexer increases from $P$-to-$1$ to $2P$-to-$1$ (Option C is affected).
4. Processor to main memory data bus: The width of this bus depends on the system architecture and the block size transferred between the cache and main memory. It is entirely independent of the internal cache associativity (Option D is NOT affected).