GATE CS 2014 Set 3 Q9 — Instruction Pipelining

The clock cycle time ($T_{\text{clk}}$) of a pipelined processor is determined by the latency of its slowest stage plus any pipeline register overhead. Since the pipeline registers have zero latency, the clock cycle time is simply the maximum stage latency of the pipeline:

The peak clock frequency ($f$) is the reciprocal of the clock cycle time:

To find the processor with the highest peak clock frequency, we must find the processor with the minimum clock cycle time ($T_{\text{clk}}$):

• Processor P1: $$T_{\text{clk}}(\text{P1}) = \max(1, 2, 2, 1) = 2\text{ ns} \implies f(\text{P1}) = \frac{1}{2\text{ ns}} = 0.5\text{ GHz}$$
• Processor P2: $$T_{\text{clk}}(\text{P2}) = \max(1, 1.5, 1.5, 1.5) = 1.5\text{ ns} \implies f(\text{P2}) = \frac{1}{1.5\text{ ns}} \approx 0.67\text{ GHz}$$
• Processor P3: $$T_{\text{clk}}(\text{P3}) = \max(0.5, 1, 1, 0.6, 1) = 1\text{ ns} \implies f(\text{P3}) = \frac{1}{1\text{ ns}} = 1\text{ GHz}$$
• Processor P4: $$T_{\text{clk}}(\text{P4}) = \max(0.5, 0.5, 1, 1, 1.1) = 1.1\text{ ns} \implies f(\text{P4}) = \frac{1}{1.1\text{ ns}} \approx 0.91\text{ GHz}$$

Comparing the peak frequencies, P3 has the shortest clock cycle time ($1\text{ ns}$) and consequently the highest peak clock frequency ($1\text{ GHz}$).