GATE CS Computer Organization and Architecture questions

Practise Computer Organization and Architecture questions for GATE CS. Explore official PYQs and original subject-wise quizzes, check answers and view available solutions. Free, no sign-in.

Track address sizes, cache organisation and pipeline dependencies carefully. Write down the units and assumptions before computing memory access times or processor performance.

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SubjectTopicYearType

An application executes

6.4 \times 10^{8}

number of instructions in

6.3

seconds. There are four types of instructions, the details of which are given in the table. The duration of a clock cycle in nanoseconds is __________. (rounded off to one decimal place) …

Which of the following is/are part of an Instruction Set Architecture of a processor?

For a direct-mapped cache,

4

bits are used for the tag field and

12

bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no other information stored for each cache block. Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte …

Which one of the following statements is FALSE?

5

-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

Consider two set-associative cache memory architectures:

\text{WBC}

, which uses the write back policy, and

\text{WTC}

, which uses the write through policy. Both of them use the

\text{LRU}

(Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?

A given program has

25 \%

load/store instructions. Suppose the ideal

\text{CPI}

(cycles per instruction) without any memory stalls is

2

. The program exhibits

2 \%

miss rate on instruction cache and

8 \%

miss rate on data cache. The miss penalty is

100

cycles. The speedup (rounded off to two decimal places) achieved with a perfect …

The baseline execution time of a program on a

2 \mathrm{GHz}

single core machine is

100

n s)

. The code corresponding to

90 \%

of the execution time can be fully parallelized. The overhead for using an additional core is

10 ~ns

when running on a multicore system. Assume that all cores in the multicore system run their share …

Consider a computer with a

4 \mathrm{MHz}

\text{DMA}

controller can transfer

8

1

cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the

\text{DMA}

1 \%

of the processor cycles are used for …

An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-

1

2

Consider the following sequence of instructions to be executed in a pipelined processor:

\text{I 1: DIV R3, R1, R2}

\text{I 2: SUB R5, R3, R4}

\text{I 3: ADD R3, R5, R6}

\text{I 4: MUL R7, R3, R8}

Which of the …

A processor with

16

general purpose registers uses a

32

-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a

16

-bit scalar field. If

8

addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ___________.

A non-pipelined instruction execution unit operating at

2 \mathrm{GHz}

takes an average of

6

cycles to execute an instruction of a program

\text{P}

. The unit is then redesigned to operate on a

5

-stage pipeline at

2 \mathrm{GHz}

. Assume that the ideal throughput of the pipelined unit is

1

instruction per cycle. In the execution of …

A processor uses a

32

-bit instruction format and supports byte-addressable memory access. The

\text{ISA}

of the processor has

150

distinct instructions. The instructions are equally divided into two types, namely

\text{R}

\text{I}

-type, whose formats are shown below. R - type Instruction Format: \begin{array}{|l|l|l|l|l|} \hline …

3

-stage pipelined processor having a delay of

10 \mathrm{~ns}

20 \mathrm{~ns}

14 \mathrm{~ns},

for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle. The …

A keyboard connected to a computer is used at a rate of

1

keystroke per second. The computer system polls the keyboard every

10 \mathrm{~ms}

(milli seconds) to check for a keystroke and consumes

100\; \mu \mathrm{s}

(micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional …

Consider the given

\text{C}

-code and its corresponding assembly code, with a few operands

\text{U1-U4}

being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable. //C-code int a[10], b[10], i; // int is 32 bit for(i=0; i<10; i++) …

4

\text{(KB)}

byte-addressable memory is realized using four

1 \mathrm{~KB}

memory blocks. Two input address lines

\text{(IA4 and IA3)}

are connected to the chip select

\text{(CS)}

port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from

\text{IA11-IA0}

are connected …

8

-way set associative cache of size

64 \mathrm{~KB} \;(1 \mathrm{~KB}=1024\; \text{bytes})

is used in a system with

32

-bit address. The address is sub-divided into

\text{TAG, INDEX},

\text{BLOCK OFFSET.}

The number of bits in the

\text{TAG}

is ___________.

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

\text{WB}

\text{WT}

be two set associative cache organizations that use

\text{LRU}

algorithm for cache block replacement.

\text{WB}

is a write back cache and

\text{WT}

is a write through cache. Which of the following statements is/are

\text{FALSE}?