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Official PYQ · 2024Set 2 · Q51Machine Instructions and Addressing ModesNAT2 marks

GATE CS 2024 Set 2 Q51 — Machine Instructions and Addressing Modes

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A processor uses a 3232-bit instruction format and supports byte-addressable memory access. The ISA\text{ISA} of the processor has 150150 distinct instructions. The instructions are equally divided into two types, namely R\text{R}-type and I\text{I}-type, whose formats are shown below.

R - type Instruction Format:
\begin{array}{|l|l|l|l|l|}
\hline OPCODE & UNUSED & DST Register & SRC Register1 & SRC Register 2 \\
\hline
\end{array}

I - type Instruction Format:
\begin{array}{|l|l|l|l|}
\hline OPCODE & DST Register & SRC Register & \# Immediate value/address \\
\hline
\end{array}

In the OPCODE\text{OPCODE}, 11 bit is used to distinguish between I\text{I}-type and R\text{R}-type instructions and the remaining bits indicate the operation. The processor has 5050 architectural registers, and all register fields in the instructions are of equal size.

Let X\text{X} be the number of bits used to encode the UNUSED\text{UNUSED} field, Y\text{Y} be the number of bits used to encode the OPCODE\text{OPCODE} field, and Z\text{Z} be the number of bits used to encode the immediate value/address field. The value of X+2Y+Z\text{X+2Y+Z} is __________.
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Answer: 34

To find the value of X+2Y+ZX + 2Y + Z, we determine the size of each field step-by-step:

1. Size of the OPCODE Field (YY)

  • The total number of distinct instructions is 150150, equally divided into two types: 7575 R-type and 7575 I-type instructions.
  • The OPCODE uses 11 bit to distinguish between R-type and I-type.
  • The remaining bits must uniquely represent 7575 operations for each type. The number of bits required is: ⌈log⁡2(75)⌉=7 bits\lceil \log_2(75) \rceil = 7 \text{ bits}
  • Thus, the total size of the OPCODE field is: Y=1 (type bit)+7 (operation bits)=8 bitsY = 1 \text{ (type bit)} + 7 \text{ (operation bits)} = 8 \text{ bits}

2. Size of Register Fields

  • The processor has 5050 architectural registers.
  • The number of bits required to address 5050 registers is: ⌈log⁡2(50)⌉=6 bits\lceil \log_2(50) \rceil = 6 \text{ bits}
  • Since all register fields are of equal size, each register field (DST, SRC, SRC1, SRC2) takes 66 bits.

3. Size of the UNUSED Field (XX) in R-type Instruction

The total instruction size is 3232 bits. For the R-type format:

OPCODE+UNUSED+DST Register+SRC Register1+SRC Register2=32 bits\text{OPCODE} + \text{UNUSED} + \text{DST Register} + \text{SRC Register1} + \text{SRC Register2} = 32 \text{ bits} 8+X+6+6+6=328 + X + 6 + 6 + 6 = 32 26+X=32  ⟹  X=6 bits26 + X = 32 \implies X = 6 \text{ bits}

4. Size of the Immediate Field (ZZ) in I-type Instruction

For the I-type format:

OPCODE+DST Register+SRC Register+Immediate/Address=32 bits\text{OPCODE} + \text{DST Register} + \text{SRC Register} + \text{Immediate/Address} = 32 \text{ bits} 8+6+6+Z=328 + 6 + 6 + Z = 32 20+Z=32  ⟹  Z=12 bits20 + Z = 32 \implies Z = 12 \text{ bits}

5. Calculation of X+2Y+ZX + 2Y + Z

Substituting the values of XX, YY, and ZZ:

X+2Y+Z=6+2(8)+12=6+16+12=34X + 2Y + Z = 6 + 2(8) + 12 = 6 + 16 + 12 = 34

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