GATE CS Computer Organization and Architecture questions
Practise Computer Organization and Architecture questions for GATE CS. Explore official PYQs and original subject-wise quizzes, check answers and view available solutions. Free, no sign-in.
Track address sizes, cache organisation and pipeline dependencies carefully. Write down the units and assumptions before computing memory access times or processor performance.
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In a -way set associative cache, the cache is divided into sets, each of which consists of lines. The lines of a set are placed in sequence one after another. The lines in set are sequenced before the lines in set . The main memory blocks are numbered 0 onwards. The main memory block numbered must be mapped to any one of …
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are respectively. There are intermediate storage buffers after each stage …
A computer has a -, 4-way set associative, write back data cache with block size of . The processor sends addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, valid bits, modified bit and replacement bit. The size of the …
A computer has a , 4-way set associative, write back data cache with block size of . The processor sends addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, valid bits, modified bit and replacement bit. The number of bits in the tag …
Register renaming is done in pipelined processors:
An direct-mapped write-back cache is organized as multiple blocks, each size of . The processor generates addresses. The cache controller contains the tag information for each cache block comprising of the following. valid bit modified bit As many bits as the minimum needed to identify the …
Consider an instruction pipeline with four stages each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure. What is the approximate speed up of the pipeline in steady state under …
On a non-pipelined sequential processor, a program segment, which is the part of the interrupt service routine, is given to transfer bytes from an I/O device to memory. Initialize the address register Initialize the count to 500 LOOP: Load a byte from device Store in memory at address given by address register Increment the address register Decrement …
Consider a hypothetical processor with an instruction of type , which during execution reads a word from memory and stores it in a register . The effective address of the memory location is obtained by the addition of a constant and the contents of register . Which …
A computer system has an cache, an cache, and a main memory unit connected as shown below. The block size in cache is words. The block size in cache is words. The memory access times are nanoseconds, nanoseconds and nanoseconds for cache, cache and the main memory unit respectively. …
A computer system has an cache, an cache, and a main memory unit connected as shown below. The block size in cache is words. The block size in cache is words. The memory access times are nanoseconds, nanoseconds and nanoseconds for cache, cache and the main memory unit respectively. …
A stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take clock cycle each for any instruction. The PO stage takes clock cycle for ADD and SUB instructions, clock cycles for MUL instruction and clock …
Consider a -way set associative cache (initially empty) with total cache blocks. The main memory consists of blocks and the request for memory blocks are in the following order: Which one of the following memory block will NOT be in cache if LRU replacement policy is …
Consider a stage pipeline processor. The number of cycles needed by the four instructions in stages is shown below: …
A CPU generally handles an interrupt by executing an interrupt service routine:
Consider a machine with a -way set associative data cache of size Kbytes and block size bytes. The cache is managed using bit virtual addresses and the page size is Kbytes. A program to be run on this machine begins as follows: double ARR[1024][1024]; int i, j; /*Initialize array ARR to 0.0 */ for(i = 0; i < 1024; i++) …
Consider a machine with a -way set associative data cache of size Kbytes and block size bytes. The cache is managed using bit virtual addresses and the page size is Kbytes. A program to be run on this machine begins as follows: double ARR[1024][1024]; int i, j; /*Initialize array ARR to 0.0 */ for(i = 0; i < 1024; i++) …
Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot: I1: ADD I2: Sub I3: ADD I4: STORE Memory BRANCH to Label if Which of the instructions I1, I2, I3 or I4 …
Delayed branching can help in the handling of control hazards For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false,
Consider a machine with a -way set associative data cache of size and block size . The cache is managed using virtual addresses and the page size is . A program to be run on this machine begins as follows: double ARR[1024][1024]; int i, j; /*Initialize array ARR to 0.0 */ for(i = …