Consider an instruction pipeline with four stages each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.
What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?
View worked solution
Answer: B
To find the speedup of the pipeline in the steady state, we compare the execution time of a non-pipelined implementation with the clock cycle time of the pipelined implementation.
1. Non-Pipelined Execution Time ()
In a non-pipelined system, an instruction must pass through all the combinational stages sequentially in a single cycle. The total delay is the sum of the individual stage delays:
2. Pipelined Clock Cycle Time ()
In a pipelined system, the clock cycle time is determined by the slowest stage delay plus the overhead of the pipeline register (latch delay):
3. Speedup () in Steady State
Under ideal conditions in the steady state, the pipeline completes one instruction per clock cycle (). The speedup is given by:
Thus, the approximate speedup of the pipeline is 2.5.
Free practice · Your answers on this page are not saved.