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GATE CS 2011 Q43 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

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An 8KB8\text{KB} direct-mapped write-back cache is organized as multiple blocks, each size of 32-bytes32\text{-bytes}. The processor generates 32-bit32\text{-bit} addresses. The cache controller contains the tag information for each cache block comprising of the following.

  • 11 valid bit
  • 11 modified bit
  • As many bits as the minimum needed to identify the memory block mapped in the cache.

What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?

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Answer: D

To find the total size of the meta-data memory needed at the cache controller, we first determine the address division for the direct-mapped cache.

1. Address Division

  • Processor Address Size: 32 bits32\text{ bits}
  • Cache Size: 8 KB=8×1024 bytes=8192 bytes8\text{ KB} = 8 \times 1024\text{ bytes} = 8192\text{ bytes}
  • Block Size: 32 bytes32\text{ bytes}
  • Number of Cache Blocks (Lines): Number of Blocks=Cache SizeBlock Size=819232=256\text{Number of Blocks} = \frac{\text{Cache Size}}{\text{Block Size}} = \frac{8192}{32} = 256
  • Block Offset Bits: log⁡2(32)=5 bits\log_2(32) = 5\text{ bits}
  • Index Bits: log⁡2(256)=8 bits\log_2(256) = 8\text{ bits}

The tag bits are calculated as:

Tag Bits=Address Size−(Index Bits+Block Offset Bits)\text{Tag Bits} = \text{Address Size} - (\text{Index Bits} + \text{Block Offset Bits}) Tag Bits=32−(8+5)=19 bits\text{Tag Bits} = 32 - (8 + 5) = 19\text{ bits}

2. Meta-data per Cache Block

For each cache block, the controller stores:

  • 11 valid bit
  • 11 modified (dirty) bit
  • 1919 tag bits
Meta-data per block=1+1+19=21 bits\text{Meta-data per block} = 1 + 1 + 19 = 21\text{ bits}

3. Total Meta-data Size

Since there are 256256 blocks in the cache, the total size of the meta-data memory is:

Total Size=256×21 bits=5376 bits\text{Total Size} = 256 \times 21\text{ bits} = 5376\text{ bits}

Thus, the correct option is D.

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