An direct-mapped write-back cache is organized as multiple blocks, each size of . The processor generates addresses. The cache controller contains the tag information for each cache block comprising of the following.
- valid bit
- modified bit
- As many bits as the minimum needed to identify the memory block mapped in the cache.
What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?
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Answer: D
To find the total size of the meta-data memory needed at the cache controller, we first determine the address division for the direct-mapped cache.
1. Address Division
- Processor Address Size:
- Cache Size:
- Block Size:
- Number of Cache Blocks (Lines):
- Block Offset Bits:
- Index Bits:
The tag bits are calculated as:
2. Meta-data per Cache Block
For each cache block, the controller stores:
- valid bit
- modified (dirty) bit
- tag bits
3. Total Meta-data Size
Since there are blocks in the cache, the total size of the meta-data memory is:
Thus, the correct option is D.
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