Consider an instruction pipeline with five stages without any branch prediction:
Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are respectively. There are intermediate storage buffers after each stage and the delay of each buffer is A program consisting of instructions is executed in this pipelined processor. Instruction is the only branch instruction and its branch target is If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is
View worked solution
Answer: B
To find the total execution time, we first determine the clock cycle time () of the pipeline:
Next, we identify the sequence of instructions that successfully complete execution. Since the branch at is taken to , the completed instructions are:
Since there is no branch prediction, instructions and are speculatively fetched. The branch outcome and target address are resolved at the end of the 4th stage, i.e., the Execute Instruction (EI) stage. This introduces a branch penalty of stall cycles to flush the incorrect instructions.
The total number of clock cycles required for a -stage pipeline to execute instructions with stall cycles is:
Thus, the total execution time is:
Free practice · Your answers on this page are not saved.
