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GATE CS 2010 Q49 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

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A computer system has an L1L1 cache, an L2L2 cache, and a main memory unit connected as shown below. The block size in L1L1 cache is 44 words. The block size in L2L2 cache is 1616 words. The memory access times are 22 nanoseconds, 2020 nanoseconds and 200200 nanoseconds for L1L1 cache, L2L2 cache and the main memory unit respectively.

 

When there is a miss in both L1L1 cache and L2L2 cache, first a block is transferred from main memory to L2L2 cache, and then a block is transferred from L2L2 cache to L1L1 cache. What is the total time taken for these transfers?

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Answer: C

To find the total transfer time, we determine the data path (bus) width from the L1L1 cache block size, which is 44 words.

Step 1: Transfer from Main Memory to L2L2 Cache

  • The block size of L2L2 is 1616 words.
  • With a 44-word bus width, the transfer requires 164=4\frac{16}{4} = 4 transactions.
  • Each transaction involves reading from Main Memory and writing to L2L2:
    Time per transaction=tMM+tL2=200 ns+20 ns=220 ns\text{Time per transaction} = t_{\text{MM}} + t_{L2} = 200\text{ ns} + 20\text{ ns} = 220\text{ ns}
  • Total time for MM to L2L2 transfer:
    TMM→L2=4×220 ns=880 nsT_{\text{MM} \to L2} = 4 \times 220\text{ ns} = 880\text{ ns}

Step 2: Transfer from L2L2 Cache to L1L1 Cache

  • The block size of L1L1 is 44 words, requiring exactly 11 transaction.
  • This transaction involves reading from L2L2 and writing to L1L1:
    TL2→L1=tL2+tL1=20 ns+2 ns=22 nsT_{L2 \to L1} = t_{L2} + t_{L1} = 20\text{ ns} + 2\text{ ns} = 22\text{ ns}

Step 3: Total Time Taken

Total Time=TMM→L2+TL2→L1=880 ns+22 ns=902 ns\text{Total Time} = T_{\text{MM} \to L2} + T_{L2 \to L1} = 880\text{ ns} + 22\text{ ns} = 902\text{ ns}

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