GATE EC Sequential Circuits questions

A binary ripple counter is designed to count $(0)_{10}$ to $(64)_{10}$. Which of the following is/are the number of flip-flops required to design the counter?

The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of $10$ cycles/second is applied to its clock (C) input. The frequency of the output Q (in cycles/second) is $\_\_\_\_$. (rounded off to two decimal places)

A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay. Which of the following options gives the correct binary representation $\left(b_{7} b_{6} b_{5} b_{4} b_{3} b_{2} b_{1} b_{0}\right)$ of the …

A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input $P 0$ is set to logic '$0$ ' and $P 1$ is set to logic '$1$' at all times. The timing diagram of the inputs $S E L$ and $S$ are also shown below. The sequence of output $Y$ from time $T_{0}$ to $T_{3}$ is _______.

In the circuit shown below, the $\mathrm{AND}$ gate has a propagation delay of $1 \: \mathrm{ ns}$. The edge-triggered flip-flops have a set-up time of $2 \: \mathrm{ ns}$, a hold-time of $0 \: \mathrm{ns}$, and a clock-to-$Q$ delay of $2$ ns. The maximum clock frequency (in $\mathrm{MHz}$, rounded off to the nearest integer) such that there …

​​​​​The propagation delay of the $2 \times 1$ MUX shown in the circuit is $10 \mathrm{~ns}$. Consider the propagation delay of the inverter as $0 \mathrm{~ns}$. If $\text{S}$ is set to $1$ then the output $\text{Y}$ is $\_\_\_\_\_\_$.

​​​​​The sequence of states $\left(Q_{1} Q_{0}\right)$ of the given synchronous sequential circuit is - $\_\_\_\_\_\_\_$.

The synchronous sequential circuit shown below works at a clock frequency $1 \; \mathrm{GHz}$. The throughput, in $\text{Mbits/s,}$ and the latency, in $\text{ns,}$ respectively, are

For the circuit shown below, the propagation delay of each $\mathrm{NAND}$ gate is $1 \mathrm{~ns}$. The critical path delay, in $\text{ns,}$ is______________(rounded off to the nearest integer).

In a given sequential circuit, initial states are $Q_1=1$ and $Q_2=0$. For a clock frequency of $1 \; \mathrm{MHz}$, the frequency of signal $\mathrm{Q}_2$ in $\mathrm{kHz}$, is __________ (rounded off to the nearest integer).

For the circuit shown, the clock frequency is $f_{0}$ and the duty cycle is $25 \%.$ For the signal at the $\text{Q}$ output of the Flip-Flop, _______________.

​​​​​​​The propagation delays of the $\text{XOR}$ gate, $\text{AND}$ gate and multiplexer $\text{(MUX)}$ in the circuit shown in the figure are $4\:ns$, $2\:ns$ and $1\:ns$, respectively. If all the inputs $\text{P, Q, R, S and T}$ are applied simultaneously and held constant, the maximum propagation delay of the circuit is

The propagation delay of the exclusive$-\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flip-flops is assumed to be zero. The clock ($\text{Clk}$) frequency provided to the circuit is $500\: \text{MHz}$. Starting from the initial value of the flip-flop outputs $Q_{2}Q_{1}Q_{0} = 1\;1\;1$ …

For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setup-time, and $t_{\text{hold}}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is _________$\text{MHz}$.

A traffic signal cycles from $\text{ GREEN to YELLOW, YELLOW to RED and RED to GREEN.}$ In each cycle, $\text{GREEN}$ is turned on for $70$ seconds,$\text{YELLOW}$ is turned on for $5$ seconds and the $\text{RED}$ is turned on $75$ seconds. This traffic light has to be implemented using a finite state machine $\text{(FSM)}$. The only input to …

In the circuit shown below, a positive edge-triggered $D$ Flip-Flop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate output $3.3$ volts for logic HIGH and $0$ volts for logic LOW levels. The data bit and clock periods are equal and the value of $\Delta T/T_{CK}=0.15,$ where the parameters $\Delta T$ and $T_{CK}$ are …

In the latch circuit shown, the $NAND$ gates have non-zero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed simultaneously to $P=Q=’1’$, the outputs $X$ and $Y$ are,

Consider the D-Latch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ has a $50 \%$ duty cycle and $CLK2$ is a one-fifth period delayed version of $CLK1$.The duty cycle at the output of the latch in percentage is _________.

A $4$-bit shift register circuit configured for right-shift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present state of the shift register is $ABCD=1101$, the number of clock cycles required to reach the state $ABCD=1111$ is _________.

A finite state machine (FSM) is implemented using the D flip-flop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_{B}=00,01,10$ and $11$. Assume that $X_{IN}$ is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state $Q_{A}Q_{B}=00$ and …