GATE EC 2026 Set 1 Q17 — Sequential Circuits

The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of $10$ cycles/second is applied to its clock (C) input. The frequency of the output Q (in cycles/second) is $\_\_\_\_$. (rounded off to two decimal places)

A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay. Which of the following options gives the correct binary representation $\left(b_{7} b_{6} b_{5} b_{4} b_{3} b_{2} b_{1} b_{0}\right)$ of the …

A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input $P 0$ is set to logic '$0$ ' and $P 1$ is set to logic '$1$' at all times. The timing diagram of the inputs $S E L$ and $S$ are also shown below. The sequence of output $Y$ from time $T_{0}$ to $T_{3}$ is _______.

In the circuit shown below, the $\mathrm{AND}$ gate has a propagation delay of $1 \: \mathrm{ ns}$. The edge-triggered flip-flops have a set-up time of $2 \: \mathrm{ ns}$, a hold-time of $0 \: \mathrm{ns}$, and a clock-to-$Q$ delay of $2$ ns. The maximum clock frequency (in $\mathrm{MHz}$, rounded off to the nearest integer) such that there …

​​​​​The propagation delay of the $2 \times 1$ MUX shown in the circuit is $10 \mathrm{~ns}$. Consider the propagation delay of the inverter as $0 \mathrm{~ns}$. If $\text{S}$ is set to $1$ then the output $\text{Y}$ is $\_\_\_\_\_\_$.

​​​​​The sequence of states $\left(Q_{1} Q_{0}\right)$ of the given synchronous sequential circuit is - $\_\_\_\_\_\_\_$.