GATE EC 2026 Set 1 Q39 — Sequential Circuits

A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay.

Which of the following options gives the correct binary representation $\left(b_{7} b_{6} b_{5} b_{4} b_{3} b_{2} b_{1} b_{0}\right)$ of the content of the shift register immediately after the $5^{\text{th }}$ clock transition (positive edge)?